import machine
import utime

REG_UART0_BASE = 0x3FF40000
REG_UART1_BASE = 0x3FF50000
REG_UART2_BASE = 0x3FF6E000

REG_UART_FIFO       = 0x000 #
REG_UART_INT_RAW    = 0x004 #
REG_UART_INT_STATUS = 0x008 #
REG_UART_INT_ENABLE = 0x00C #
REG_UART_INT_CLEAR  = 0x010 #
REG_UART_CLKDIV     = 0x014 #
REG_UART_AUTOBAUD   = 0x018 #
REG_UART_STATUS     = 0x01C #
REG_UART_CONF0      = 0x020 #
REG_UART_CONF1      = 0x024 #
REG_UART_LOWPULSE   = 0x028 #
REG_UART_HIGHPULSE  = 0x02C #
REG_UART_RXD_CNT    = 0x030 #
REG_UART_FLOW       = 0x034 #
REG_UART_SLEEP      = 0x038 #
REG_UART_SWFC       = 0x03C #
REG_UART_IDLE       = 0x040 #
REG_UART_RS485      = 0x044 #
# AT_CMD... 0x48,0x4c,0x50,0x54
REG_UART_MEM_CONF   = 0x058 #
REG_UART_MEM_CNT_STATUS = 0x064 #
REG_UART_POSPULSE       = 0x068 #
REG_UART_NEGPULSE       = 0x06C #


# UART INT Registers Bits
UI_XOFF= 10 # Software XOFF
UI_XON = 9  # Software XON
UITO   = 8  # RX FIFO TimeOut
UIBD   = 7  # Break Detected
UICTS  = 6  # CTS Changed
UIDSR  = 5  # DSR Change
UIOF   = 4  # RX FIFO OverFlow
UIFR   = 3  # Frame Error
UIPE   = 2  # Parity Error
UIFE   = 1  # TX FIFO Empty
UIFF   = 0  # RX FIFO Full

# UART CLKDIV
U_CLKDIV = 0
U_CLKDIV_FRAG = 20

# UART STATUS Registers Bits
USTX   = 31 # TX PIN Level
USRTS  = 30 # RTS PIN Level
USDTR  = 39 # DTR PIN Level
UART_ST_UTX=24 # (4b)
USTXC  = 16 # TX FIFO COUNT (8bit)
USRXD  = 15 # RX PIN Level
USCTS  = 14 # CTS PIN Level
USDSR  = 13 # DSR PIN Level
UART_ST_URX_OUT=8 # (4b)
USRXC  =  0 # RX FIFO COUNT (8bit)

# UART CONF0
UART_TICK_REF_ALWAYS_ON = 27
UCDTRI  = 24 # Invert DTR
UCRTSI  = 23 # Invert RTS
UCTXI   = 22 # Invert TX
UCDSRI  = 21 # Invert DSR
UCCTSI  = 20 # Invert CTS
UCRXI   = 19 # Invert RX
UCTXRST = 18 # Reset TX FIFO
UCRXRST = 17 # Reset RX FIFO
UCTXHFE = 15 # TX Harware Flow Enable
UCLBE   = 14 # LoopBack Enable
UCBRK   =  8 # Send Break on the TX line
UCSWDTR =  7 # Set this bit to assert DTR
UCSWRTS =  6 # Set this bit to assert RTS
UCSBN   =  4 # StopBits Count (2b) 0:disable, 1:1bit, 2:1.5bit, 3:2bit
UCBN    =  2 # DataBits Count (2b) 0:5bit, 1:6bit, 2:7bit, 3:8bit
UCPAE   =  1 # Parity Enable
UCPA    =  0 # Parity 0:even, 1:odd

# UART CONF1 Registers Bits
UCTOE   = 31 # RX TimeOut Enable
UCTOT   = 24 # RX TimeOut Treshold (7bit)
UCRXHFE = 23 # RX Harware Flow Enable
UCRXHFT = 16 # RX Harware Flow Treshold (7bit)
UCFET   =  8 # TX FIFO Empty Treshold (7bit)
UCFFT   =  0 # RX FIFO Full Treshold (7bit)


REG_GPIO_PIN_BASE = 0x3FF44088
REG_IO_MUX_GPIO16 = 0x3FF4904C
REG_IO_MUX_GPIO17 = 0x3FF49050

#print(machine.mem32[REG_UART0_CONF1]>>UCFET & 0x7f)
print("HELLO, WORLD!")
#machine.mem32[REG_UART0_INT_ENABLE] = machine.mem32[REG_UART0_INT_ENABLE] | 1<<UIFE
#print(machine.mem32[REG_UART0_INT_STATUS]>>UIFE & 0x1)

def uart2_enable():
    RXD_MUX = machine.mem32[REG_IO_MUX_GPIO16]
    RXD_MUX &= 0b11111111111111111100011111111111 # Clear function selection
    RXD_MUX |= (5-1) << 12 # Set function(5)
    RXD_MUX |= 1 << 9 # Input enabled
    RXD_MUX |= 1 << 8 # Pullup enabled
    print(hex(RXD_MUX), bin(RXD_MUX))
    machine.mem32[REG_IO_MUX_GPIO16] = RXD_MUX # Set RXD_MUX
    # Signal  Input       Output      Direct-IO_MUX
    # 198     U2RXD_in    U2TXD_out   YES
    machine.mem32[0x3FF44130+0x4*198] = 16 | 1<<7 # SIG_IN_SEL
    print(machine.mem32[0x3FF44130+0x4*198])
    
    TXD_MUX = machine.mem32[REG_IO_MUX_GPIO17]
    
print(hex(machine.mem32[REG_IO_MUX_GPIO16]))
uart2_enable()

def n2uart(u):
    if u == 0:
        return REG_UART0_BASE
    elif u == 1:
        return REG_UART1_BASE
    elif u == 2:
        return REG_UART1_BASE

APB_CLK=80000000

def uarttxq(u):
    return machine.mem32[n2uart(u)+REG_UART_STATUS]>>USTXC & 0xff
#bin(machine.mem32[n2uart(2)+REG_UART_STATUS]&0x7fffffff)
def uartrxq(u):
    return machine.mem32[n2uart(u)+REG_UART_STATUS]>>USRXC & 0xff

def uartbaud(u, new=None):
    if new:
        clk_div = round((APB_CLK<<4) / new)
        machine.mem32[n2uart(u)+REG_UART_CLKDIV] = (clk_div >> 4) | ((clk_div & 0xf) << U_CLKDIV_FRAG)
    clk_reg = machine.mem32[n2uart(u)+REG_UART_CLKDIV]
    return (APB_CLK<<4) / (((clk_reg & 0xfffff) << 4) | ((clk_reg >> U_CLKDIV_FRAG) & 0xf))

def uartsync(u):
    while uarttxq(u): utime.sleep_us(8)
    utime.sleep_ms(10)
    
print("U0TXQ", uarttxq(0))
print("U0RXQ", uartrxq(0))
print("U0BDR", uartbaud(0, 115200))

print("U2TXQ", uarttxq(2))
print("U2RXQ", uartrxq(2))
print("U2BDR", uartbaud(2, 9600))


"""
u = machine.UART(0)

gps = machine.Pin(4, mode=machine.Pin.OUT, value=0)

print(u)
print(dir(u))
u.write('test\n')

uartsync(0)
u.init(baudrate=9600, timeout=10000)

gps(1)
line = u.read(100)
gps(0)

uartsync(0)
u.init(baudrate=115200)

print(line)
"""